Yes. CVC routinely outperforms all other commercial simulators by a factor of 2 and up to 20X for RTL and gate level simulations. Sign up for a free evaluation and see CVC's superior peformance for yourself.

You are probably in the wrong place, but you can check out the Wikipedia entry on Verilog simulators.

Currently CVC runs on X86 architecture Linux and Apple Mac OS X systems. It comes in 32 and 64-bit versions. There is no support for Windows at this time. If you are interested in a specific OS or architecture please contact us for possible support.

Sign up for an evaluation. We would be happy to set you up to see CVC's performance on your design.

To learn more about how CVC with X-propagation can save you valuable design debugging time visit the X-propagation page.

First, CVC will probably run your design faster than your current simulator. If simulation speed is critical for your large design it makes sense to evaluate CVC. This is also true for designs which are on the verge of having to use expensive emulation products because the simulator is not up to speed or requires too much memory.

Second, it is good to verify a design's correctness on multiple simulators. Subtle differences in simulators help expose design flaws and race conditions. Adding CVC licenses to assure that your design is correct is a small price to pay.

Third, CVC has many unique features which set it apart, including X-propagation which can save valuable design debugging time.

Lastly, the "all you can eat" or the "we'll give you a discount to use us as your single EDA vendor" business model is not good for innovation in the EDA industry as a whole and not good for you as a consumer of EDA products.

Using CVC and its initial setup is simple. It is a single self contained binary, there are no complex installation or environment variables necessary to get CVC up and running. CVC's simple one step compilation is simple and does not require complex libraries or scripts which add to the complexity of running other simulators.

Yes. CVC has full support of the Verilog Programming Language Interface (PLI). Full support for PLI (vpi_*, acc_*, tf_*) routines. CVC has faster and more robust VPI support because it has been used to implement the digital part of complex mixed signal tools. CVC also supports the SystemVerilog Direct Programming Interface (DPI) for directly interfacing with C/C++/SystemC.

Yes. CVC now supports the SystemVerilog Direct Programming Interface (DPI).

No. There are no immediate plans to add a GUI. If you chose your EDA tools based on a GUI the we suggest you look else where. We are concentrating our efforts on providing the fastest Verilog simulator on the market and adding more SystemVerilog features.

We do not directly provide a waveform viewer. However, we support both the standardized VCD/EVCD wave form dump format plus some formats with better data compression. CVC supports the FSDB format which is used with Springsoft's (Novas) line of tools, and GTKWave's FST fast compression format. Both compressed formats solve the VCD/EVCD large dump file problems.

Yes. CVC has built in coverage metrics to gauge your design's test coverage.

CVC supports the full 2005 IEEE 1364 standard and some SystemVerilog. CVC also contains other add on features in addition to the IEEE 1364, but all standard features are supported. We are always interested in adding features to further improve CVC. If you have something particular in mind feel free to contact us about adding support.

No, strictly Verilog/SystemVerilog. We have no intentions of supporting VHDL at this time. We are concentrating our efforts on adding more SystemVerilog features.

Currently CVC supports SystemVerilog variable types (including 2-state), DPI, C-style constructs lacking in 2005 Verilog, etc. We are working on support for additional SystemVerilog features.

Yes, you can use the SystemVerilog DPI to directly interface SystemC.

Unfortunately not at this time. We currently don't have resources to offer support for a lesser version. We only have one full capacity, high speed professional version.

Verilog simulation is a time proven approach used in the design and verification of the world's most complex chips. While many new higher level ESL languages are under development to simplify system design and verification, Verilog remains the backbone of digital design.

CVC's unique ability to run in either compiled mode or interpreted mode has significant advantages. Interpreted mode allows for fast elaboration of large designs during the initial design phase, essentially eliminating compilation to machine code setup and time. Then when simulation speed is important, CVC compiles into a native binary that executes faster than any available simulator.

Yes. We have been working on Verilog simulators almost as long as Verilog itself. We have an extensive regression suite with thousands of unit tests, designs with millions of lines of Verilog for performance testing, and a random test generation system which allows infinite testing to assure CVC's correctness.

We are always interested in new ideas and opportunities, please contact us with any potential ideas.

Well at least we got you here, right? We have an engineering staff and tight R & D budget, not a large marketing budget and staff of a Mentor/Cadence/Synopsys. What we do have is a Verilog simulator which can out perform theirs. Sign up for an evaluation and see for yourself.

A Tachyon is a particle which moves faster than light, check the Wikipedia Tachyon page for more information. We chose the name to illustrate the speedy simulations and superior performance of CVC.