CVC Verilog Simulator Benchmarks

Below are CVC simulation times for various Verilog designs you can download and run. Designs and simulation times are provided to illustrate CVC's unmatched price/performance.

If you simply want to see CVC's performance compared to other simulators on one design, please visit the Verilator benchmarks page.

To run the benchmarks on CVC or any other Verilog simulator, simple click on 'source' to download the Verilog source and pass in the Verilog file list (usually with -f run.flist) to the simulator. Designs are from www.opencores.com with minor modifications so that they are easy to run on any simulator. Listed CVC simulation times were run on an Intel i5 2500k 3.3 Ghz processor.

Designs and Simulation Times
DESIGN NAME CVC OPTIONS TIME (seconds) Download
usb1.1 -O 2.5 download
m68k (Verilator benchmark) -O +nbaopt 10.3 download
ata -O 17.8 download
ac97 -O +nbaopt +2state 39.2 download
can -O 5.5 download
sha1 -O +2state 0.9 download
ethernet -O 113.7 download
generic_fifos -O +nbaopt 100.4 download
wb_dma -O +nbaopt +2state 788.3 download

For example to run the usb11 open core design with CVC:

%unzip usb11.zip
%cd usb11
%cvc +verbose -f run.flist
%cvcsim

All example design source directories have a 'run.flist' standard Verilog -f option argument that contains the list of files needed to run the simulation. A 'cvc.log' file is also present in the top level of the directory. It contains expected simulation results and times. For CVC, you need to use the +verbose option so that compilation, simulation and loading times are printed.