Tachyon Design Automation's flagship product, CVC, is a Verilog Hardware Description Language (HDL) simulator. CVC's fast native compilation technology provides industry leading performance and capacity. CVC's superior performance along with its flexible pricing, makes it a valuable yet cost efficient tool to add to your existing IC design flow. Increase your simulation throughput to meet your design team's simulation needs. CVC's fast fully accurate software simulation can reduce your time to market while reducing your verification costs.

CVC supports the complete 2005 IEEE 1364 Verilog HDL Standard and includes some additional SystemVerilog features. More SystemVerilog features are under currently under development and will be released in future versions.

CVC has new X-propagation features that detect possible X value bugs at RTL level, eliminating the need to debug at gate level. Visit the X-propagation section for more information on the advantages of CVC's unique features.

CVC Advantages -

• Fast native compiled simulation.
• Lower cost with enhanced performance.
• Unique X-propagation features.
• Linux X86 and Apple Mac OS X support.
• Ability to simulate in either compiled or interpreted mode.
  • Interpreted mode allows for fast elaboration of large designs during the initial design phase. Flow graph machine code generation and optimization steps are removed to speed up elaboration.
  • Then when simulation speed is important, CVC compiles into a native binary that executes faster than any available simulator.
• Built in Coverage.
• Large gate and RTL capacity.
• Notebook friendly and flexible licensing.
• VCD/EVCD/FST/FSDB design state dump formats.
• SystemVerilog DPI support.
• Full PLI (vpi_*, acc_*, tf_*) support.
• Fully IEEE Verilog 1364-2005 standard compliant.
• Get both 32/64-bit versions for one price.
• 2-state simulation.