Tachyon DA's simulator, CVC, contains a set of unique X-propagation features which expose bugs at RTL level, helping to eliminate the need for costly gate level debugging. Here we briefly describe the problem, the solution, and CVC's advantages over existing products. We encourage you to sign up for an evaluation to learn more about CVC X-propagation and how it can save your team valuable time.

- The problem: Verilog X Issues -

Standard RTL Verilog semantics treat Xs as 1s or 0s due to X-optimism or X-pessimism. This causes real bugs to go undetected resulting in X-bugs only showing up after synthesis during gate level simulations or even worse as they slip by completely on the way to tapeout. This lack of accuracy allows design flaws to remain undetected in RTL level Verilog. The problem forces designers to debug using post-synthesis gate level simulation. Debugging designs during slow gate level simulation is difficult and puts a strain on engineering resources which can delay getting products to market.

- The solution: CVC's X-propagation features -

CVC's new X-propagation features changes Verilog semantics so that unknown values are treated as having potentially all possible Verilog values 0, 1, or X. This causes propagation of unknown (X) values if any possible value choice can result in an unknown (X). The new technology is a game changer because it allows normal RTL model verification methods to detect a type of systems on a chip (SoC) bug that was previously undetectable.

CVC's X-propagation enhancement is a number of options and recording mechanisms that change the semantics of standard Verilog allowing designers to locate, evaluate and fix potential X value bugs during RTL simulation. CVC's X-propagation finds bugs during RTL simulation which are undetectable using formal methods and previously could only be found during gate level simulation. These new features requires no changes to existing Verilog RTL designs and allows using existing design test benches.

- CVC X-propagation Advantages -

  • Requires NO changes to existing Verilog designs.
  • Quickly computes all possible values when Xs occur and propagates X values at RTL level.
  • Reports when/where conditional Xs occur for simple debugging.
  • Since it is done during actual simulation it finds problems which formal tools cannot.
  • Fast X-propagation during simulation. CVC's X-propagation overhead is less than 30% on real designs on top of CVC's industry leading performance.
  • Eliminates difficult gate level debugging.
  • CVC X-propagation prevserves X's that are really 'don't cares' used to improve synthesis results.

To learn more about CVC's X-propagation sign up for an evaluation today.

Overview
During a design cycle inconsistencies arise between Verilog RTL and gate level simulations. These inconsistencies result in having to debug at gate level when tracing Xs is slow and difficult. CVC's X-propagation features solves this problem by adding a set of unique features which help detect and debug the source of Xs at RTL level.