Learn More About CVC

1. Quick Start Guide

Not ready to download OSS CVC?  It is best to download CVC because the release directory has extensive documentation and examples.   Click to download the CVC quick start guide.


2. Semiwiki Customer CVC Speed Evaluation

Also, it is best to download OSS CVC and run the included open core models to evaluate CVC speed. However, you can download an evaluation of CVC performance by an CVC RTL only user published on the Semiwiki site.

Semiwiki CVC evaluation

3. Dan Joyce Argument for Gate Level Simulation from Deepchip

The EDA blog space is full of posts arguing that gate-level digital Verilog model simulation is no longer required. An interesting counter argument on the importance of gate-level simulation has been posted on Deepchip by Dan Joyce.

In his post Joyce lists 16 bug types only found by using gate-level simulation.

Gate-level bugs

The next three posts are Joyce’s tips for cost effective gate-level simulation.

Gate-level Tips (pt 1)

Gate-level Tips (pt 2)

Gate-level Tips (pt 3)

Gate level simulation in CVC has minimal overhead because CVC implements multiple instances of modules and gates using one machine code model plus per instance net data. Also CVC compiles the event queue to lessen overhead from the extra events needed by gate level simulation.

CVC implements all the IEEE 1364 Verilog gate level simulation constructs. Gate level compile time is not larger in CVC. RAM use by the cvcsim binary are usually only 2 or so times larger because CVC does not flatten. Even if all nets in a design are dumped to an FST file, overhead is only 50% if the +fst+parallel2=on option is selected (not recommended dumping all nets because the .fst file will be rather large).

Do not use any option that turns off specify block simulation (avoid +mipdopt, +nospecify and +notimingchecks). You can still use the+nbaopt option if your design allows it.

You should select some combination of the +show_canceled_e and +pulse_e_style_ondetect options, but do not use the +warn_canceled_e option for large simulations.

To initialize nets and memories to random values use the CVC option +random[=optional seed] or +random_2state again with optional seed.

4. Scientific Paper Describing CVC Compiler Internals

If you are interested in the compiler development innovations in CVC, you can read this scientific paper.   It uses a method derived from Karl Popper’s falsifiability that is currently not accepted by academics.   Paper  describes CVC compiler design methodology, general organization and Verilog machine code generation innovations.


5. Unsubscribe from CVC Mailing List

Currently the only way to re-download OSS CVC if you have already subscribed is to unsubscribe from our mailing list and then re-subscribe.