CVC is a full IEEE 1364 2005 compliant Verilog Hardware Description Language (HDL) simulator that compilesVerilog to native X86_64 machine instructions which are executed as a simple native Linux binary. CVC is as least as fast as any commercial full 1364 2005 simulator.
- Fast native compiled simulation.
- Very large gate and RTL capacity with 64 bit CVC64. 64 bit simulation is faster than 32 bit on modern hardware at the cost of larger cvcsim binary files.
- Best solution for machine generated Verilog simulation.
- Implements new X-propagation synthesizable Verilog expression evaluation algorithm.
- Linux X86 support.
- Ability to simulate in either compiled or interpreted mode.
- Interpreted mode allows for fast elaboration of large designs during the initial design phase. Flow graph machine code generation and optimization steps are removed to speed up elaboration.
- Then when simulation speed is important, CVC compiles into a native binary that executes faster than any available simulator.
- Built in toggle coverage with per instance/bit and tick period control.
- VCD/EVCD/FST design state dump formats.
- Latest FST output for close GTKWave integration. Options that allow using up to 2 additional X86 cores for parallel FST generation.
- Full PLI (vpi_*, dpi_*, acc_*, tf_*) support.
Fastest vpi_ and no overhead dpi_ ABI interface to c/c++.
- Fully IEEE Verilog 1364-2005 standard compliant.
- 2-state simulation.
- C compiler style simple compilation to executable – no projects and no 3 step design loading.